The present invention relates to a saddle fin transistor having an elevated landing plug contact and manufacturing method of the same.
In a photolithography process (one of many processes for manufacturing a semiconductor device), a photomask for forming a pattern is and essential requirement. The photomask includes a mask pattern which defines various elements of semiconductor device. The size of mask pattern elements becomes gradually smaller (i.e., density increases) according to the integration of the device. The channel length and channel width of transistor are reduced as the design rule of the semiconductor device is reduced. Consequently, in attaining the threshold voltage Vt required in a high integration semiconductor device, the conventional planar transistor structure is confronted with a limit. In order to overcome this limit, various types of transistors are suggested, and one of them is a fin transistor.
FIG. 1 is a drawing illustrating the structure of conventional fin transistor.
A fin transistor is formed in such a manner that an active region 11 of a semiconductor substrate 10 is formed to be protruded than an isolation layer 12 while a gate electrode 13 is formed cross over the protruded active region 11. In the fin transistor, the channel width of a transistor is increased as much as the protruded height such that the current drivability can be improved and the operation speed can be increased.
However, in case of the fin structure, the junction leakage current can be increased due to the enlargement of the channel region. Accordingly, the fin structure has some drawbacks when applied to a cell transistor which requires a sufficient data retention time.
FIG. 2 is a drawing which schematically illustrates the structure of a recess transistor which has been proposed to secure a data retention time.
In the recess transistor, a semiconductor substrate 20 of a gate 22 region is etched with a given depth, so that the distance between the source and the drain is extended.
However, such a recess transistor can secure a data retention time but the current drivability is not as good as the fin transistor.
Accordingly, the Saddle Fin FET has been recently proposed, which implements features of the fin transistor and the recess transistor within one cell to have both the current drivability of the fin transistor and the data retention time of the recess transistor.
FIG. 3 is a drawing illustrating the structure of conventional saddle fin transistor.
The saddle fin transistor has a channel region of recess structure in which an active region 31 of a semiconductor substrate 30 is etched to a given depth in a gate region, while having the structure in which the isolation layer 32 is more etched than the channel region such that the channel region has a protruded structure. The protruded channel region is named as a saddle fin.
Since the saddle fin transistor secures a stable refresh characteristic with the recess gate structure and the floor side of the recess gate is formed with the fin structure, the width of the channel is increased and current drivability is improved.
However, during the manufacturing process for the saddle fin transistor a significant amount of isolation layer needs to be etched. Thus, the misalign of gate can be generated. Further, if the isolation layer is not sufficiently strong, as shown in FIG. 4, during the forming of the landing plug contact (LPC), the landing plug contact (LPC) self aligned contact (SAC) fail can be generated within the isolation.
Recently, instead of a conventional HDP (High Density Plasma) insulating layer, the SOD (Spin On Dielectric) insulating layer has been used as an isolation layer. The SOD insulating layer has a better gap fill characteristic, so that the gap fill between the active regions can be better performed.
However, with the SOD insulating layer, since the etch rate in the wet etching is very high in comparison with the HDP insulating layer, the occurrence of the above problem (see FIG. 4) can be increased.
Moreover, due to the loss of the SOD insulating layer, the gap between field isolation regions is reduced. This can cause an increase in the signal interference phenomenon which affects a main gate arranged in an active region by a passing gate arranged on the SOD insulating layer (isolation layer).
Consequently, the GIDL (Gate Induced Drain Leakage) current is increased such that the short channel margin of transistor is reduced. Particularly, in the DRAM device, since the data retention time is reduced and the normal operation becomes difficult, the yield and reliability of the device are lowered.